[Cs35101] hw6 question 1, figure not clear

[Dianne Foreback]

Dear Computer Architecture Class:

The figure 4.2 from the book for homework 6, problem 1, is not clear.  We
cannot assume that 0 represents the selector value at the top of the
multiplexers and 1 represent the selector at the bottom in regards to
controlling the input into the PC (see Figure 4.33 for the mux settings.

To understand the signals that need to be set, later figures of the single
cycle datapath, Figure 4.15 with signal names and effects in Figure 4.16
provide a clearer picture.  Examining these figures, for the AND
instruction: RegDst should be asserted to select register rd as the
destination register; ALUSrc should be set to 0 to read data 2 from the
register file to use the rt register; PCSrc should be deasserted to
increment the PC by 4; MemRead and MemWrite are deasserted since the AND
instruction uses only registers rs, rt and rd and does not store or load
data from memory; MemtoReg is deasserted so that the write data to register
rd will be fed from the ALU.  The ALUOp is 10 (because AND is an R-format
instruction) and the ALU control is 0000 for the AND instruction.
Furthermore, examining figure 4.17, Branch is deasserted.

So, I am giving 5 points on question 1 to all who turn in their homework
6.  However, for your knowledge, please read the answer given above.

Sincerely,
Dianne


_______________________________________________
Dr. Dianne Foreback, Assistant Professor
Department of Computer Science
Math and Computer Science Building (MSB) 266
P.O. Box 5190, Kent, Ohio 44242-0001, USA
Phone: 330.672.9064
Email: dforebac at kent.edu
_______________________________________________
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